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Features
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Operates as Host or Device Bridge Between Serial ATA and Parallel ATA interfaces Ultra ATA100 Mode Supported with Rates up to 100 MB/s Data is Transferred on Both Edges of the STROBE when in Ultra DMA Mode 16-bit CRC is Calculated on a Per-burst Basis Ultra DMA5 Compliant Drive Interfaces Compatible with 48-bit LBA Methods of Addressing Dual 1024-byte Transmit/Receive FIFO for Overrun Prevention 8B/10B Encoding and Decoding in Serial ATA Link Layer Low Power: < 380 mW Supports PIO Modes 0, 1, 2, 3 and 4 Supports UDMA Modes 0, 1, 2, 3, 4, and 5 Supports 80-conductor Cable for UDMA Modes 4, and 5
Overview
The AT78C5010 SATA Controller bridges the conventional Parallel ATA devices with Serial ATA PHY transceivers. It includes a Serial ATA Link layer, a Transport layer, a Command Layer, two 256 x 32 FIFOs and an IDE Host/Target Controller, a Serial ATA Core and an IDE Controller, and is fully compliant with Serial ATA Gen1. The PHY block is connected to the ATA block by a 20-bit transmit and a 20-bit receive data bus. The bridge is intended to adapt an Ultra ATA100 Disk drive to a Serial ATA Host interface, and a Serial ATA Device interface to Ultra ATA100 Host interface. Ultra DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED, and PACKET commands.
Serial ATA Host/Device Bridge AT78C5010 Summary
3480BS-NETST-8/04
Note: This is a summary document. A complete document is available under NDA. For more information, please contact your local Atmel sales office.
Figure 1. AT78C5010 Block/PAD Interconnect
Alternate PHY Test Pin Functions Rx[19:0], Receive Data Bus RX+ RXTx[19:0], Transmit Data Bus TBC (transmit byte clock 75 MHz) RX+ RXTX_ENABLE RBC (receive byte clock 75 MHZ) COMMA_DETECT REALIGN COMWAKE COMRI 1.5Gb/s Transceiver PARTIAL SLUMBER STOP RESET RX_LOCKED RX_ERROR SCLK SDEN SDATA ASIC_CKRATE ASICLK ATA/Serial ATA Controler ATA_PDIAGN ATA_DASPN ATA_CS ATA_INTRQ ATA_DMARQ ATA_DMACKN ATA_RESETN ATA_HOST SCLK TEST_MUX0 SDEN TEST_MUX1 SDATA TEST_MUX2 EEPROM TEST_MUX3 TEST_ENABLE0N TEST_ENABLE1N TEST_ENABLE2N XTAL_IN XTAL_OUT PHY_SLOP PHY_DATA[19] PHY_SLV PHY_RXLOCKED PHY_DIRECTION ATA_DATA[15:0] ATA_ADR[2:0] ATA_IOWRN ATA_IORDN ATA_HCS0 ATA_HCS1 ATA_IOCHRDY PHY_COMDET PHY_DATA[15:] PHY_DATA[18:16] PHY_TBC PHY_RBC
PHY_SCLK PHY_SDEN PHY_SDATA PHY_EWRAP
OSC AMP
RESET COMPARE
PRESETN
PHY_RESET
2
AT78C5010
3480BS-NETST-8/04
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3480BS-NETST-8/04

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